Patrick Donaldson: A Shameless Self Portrait

Much of how I acquired skills as a career Electronic Engineer has been by good fortune, but I took advantage of what good fortune came my way, shook off the bad fortune and worked it into a good career and satisfying life.
It started with a simple teenage boy who became an electronic hobbyist after receiving a Radio Shack 150 in 1 Electronic Project Kit as a Christmas gift at 13.  This gift from Mom and Dad, most certainly influenced by my father as a reward for helping with the Christmas lights and encouragement for future exploration for an observed inborn interest and possible skill.  He taught me the difference between a series and parallel circuit years before and worked on the simple version of ohms laws until I finally got it.

150 in One Electronic Project Kit

The Beginning
After learning how to play guitar (poorly) I began working on repair and then modifying and customizing solid state and tube guitar amps, as well as those little effects, stomp boxes.  This was ten times the fun of the 150 in 1 kit!  (There’s a bad math joke in there, let’s ignore it.)

Fender Blues Deluxe Tube Guitar Amp

3 x 12AX7 and 2 x 6L6 tube complements; solid-state rectifier
At 18 I joined the Navy and signed up for the advanced 6-yr Electronics Tech (ET) program, 2-yrs of 50 hr/week training followed by 4-yrs of fleet service.  We mainly worked with repairing and maintaining Navy  Comm systems and RADAR. The RADAR equipment we trained on was the tried and true AN/SPS10-10The training units were the first or among the original releases, long since put to pasture and maintained by the training staff.  they all used tubes as active components almost exclusively!  The original SPS-10 emitted 190 or 285 kW pulses. This radar was retired from service at the end of 1998. The AN/SPS 10B was replaced by the AN/SPS 502 in some ships and kept the same antenna.
The AN/SPS-10 was a medium range, C-Band surface search radar. It was used for the detection, ranging and tracking of surface contacts and to a limited extent, air contacts as well.
The communication equipment was more modern and only had tubes in the RF transmission and sometime IF stages.
Unfortunately (but as it worked out, not so unfortunately) a motorcycle accident  cut my Navy career in half after 3-yrs and after a year of recuperating from two open, compound fractured femurs and compound fractured hip, I went to work as an electronic tech and started to beef up my academics at night so that I could get into a good engineering program.
During that time I worked as a tech in seemingly every possible discipline in existence  from digital circuits with microprocessors using emulators, logic analyzers (in addition to the standard O’scopes, meters etc.)  purely analog circuits, mixed-signal circuits, I picked up C-programming, worked on microwave circuits with the Hewlett-Packard microwave test equipment (scalar and network analyzers which have changed very little in their basic configuration to this day, only with more accuracy and a few more functions.)
After 4 years of working as a tech, I was accepted to attend the University of Massachusetts @ Amherst where I graduated in 1994 with a BSEE with minors in Mathematics and Physics.   After graduating and fortuitous recruitment by Raytheon TSD (Test Systems Division) the engineering phase was underway!  The diversity of my experience helped in getting a leg up on my fellow college hires and I was mercifully pulled out of the indoctrination program early to do real work (as opposed to the standard time spent learning the company culture and how to look up and edit parts in inventory etc.)  Bona-fide engineering work developing the test system(s) for the MILSTAR  (Military Strategic and Tactical Relay) equipment. Again, the areas of electronic disciplines used were diverse.   Microwave for the satellite transmission and lots of lower frequency (non-RF) communication parts for MILSTAR.
MILSTAR Sattelite

And now for some foreshadowing.  An engineer’s awareness and knowledge of the challenges in the operational environment of space is critical such that the design is tested to the limits of a mission without requiring expensive overdesign.  Planning for such designs which use microelectronic components and assemblies in space environments requires adherence to strict guidelines.  Much of what was learned by NASA has been passed down to the avionics community.  The characteristics of a variety of environments, relevant to both Earth and space scientific, military and commercial missions, are enveloped within typical representative parameters:  Radiation, Thermal, Vibration, Electrostatic, Electromagnetic, and Electrical environments.  Early on these lessons were learned from working with the MILSTAR program.  There are standards and guidelines which must be adhered to.   Many companies have their own standards regarding coding style for software and HDL languages, safety procedures and of course design standards (such as design to test etc.)

Then there are Military, Commercial, Medical and other standards, too numerous to mention.  My introduction to Design assurance and reliability came as part of the package and I learned it is essential to being a designer of electronic systems.  Mil-Std for reliability (MIL-HDBK-217), (HBK-HW-55) and BIT Design Process (HBK-SYS-9) RTCA DO-254

Earth’s magnetic field, also known as the geomagnetic field, is the magnetic field that extends from the Earth’s interior out into space, where it meets the solar wind, a stream of charged particles emanating from the Sun.
 I wound up on the design team for the APATS (Antenna Pedestal Assembly Test System).  The APATS test system allowed the depot operator to automatically detect and fault isolate defects within the MILSTAR antenna pedestal assemblies.  For the APATS system, the circuit cards were mounted in the Hewlett Packard’s extension of the standard VME chassis they calledVXI.  Some of these circuit cards were COTS equipment (Commercial Off The Shelf) such as the single board computer (SBC) which controlled the chassis functionality (it’s called the slot ‘0’ controller) and many of the basic instrumentation cards like multi-input micro-ohm meters and data acquisition cards etc.  Of course being the junior engineer I was tasked with the procurement of these COTS parts to my chagrin, but as I learned,  parts procurement for a project is an important part of the design process.  More good experience.


Antenna Pedestal Assembly Test Station
The COTS VXI cards only covered a fraction of our testing needs and as the project moved along, requirements for custom circuit cards were required for test coverage.  There were seemingly miles of wiring and transmission lines interfacing the APATS test system to the Antenna equipment.  Due to the lack of personnel with any digital experience on the small APATS test system group, I was tasked to do design some circuitry for a couple of stim boards which were predominantly digital but were definitely mixed signal having analog circuitry like op-amps and some MOSFET and bipolar transistors.  Not the highest tech work in the house; however,  it was design work and getting design work early in your career is important if you ever hope to be a designer.  The APATSprogram was completed in 1996, but has evolved and still is in existence in the Army.
APATS: MILSTAR Airborne antenna
To add some dark humor, one of the digital guys left for a higher paying job and a senior guy who was one of the project leads (there were several on MILSTAR) died of a heart attack in his office.   It was a sad time, but the job had to be done and his office was pilfered by many of the veteran staff of the shortly after his untimely death because Raytheon was so competitive.  People did what they had to do to get a good project.  One of these pilfered projects had a board with a CPLD on it.  I was the only one left in that small (and shrinking) group who had any experience whatsoever with a programmable device.  I only used a PLD in the “Intro to Computer Systems” class at UMASS, mostly on paper with the only “hands-on” experience being in the lab portion for 2 or 3 labs.  I had never actually designed any circuitry with one as a professional, so it was there that my career in programmable digital hardware began.  The project with the PLD  was on the  PAC-III project.   The simulator was a Teradyne ATE (Automatic Test Equipment).  This is long since been obsolete.

There was some motor controller testing in this group and something called Kalman Filters in the tracking system. These filters have many uses in motion tracking and are great for trajectory optimization for missiles,  but also has many other uses such as Econometrics. There was a Principal Engineer Dr. Eli Bruchner on staff at Raytheon who taught a class to our group once a week.  This work was at the forefront of signal processing technology.

Raytheon PAC III In Action
A cutaway diagram in Russian?
Dr. Eli Brookner

Taught the Class: “Kallman Filters as Your Friends!”

Warren White Award for Excellence in Radar Engineering, IEEE Centennial Medal, IEEE Millennium Medal, IEEE Educational Activities Board Meritorious Achievement Award
                  Eli’s Favorite Circuit!
Kalman Filter: Predict, Measure, Update, Repeat
Dr. Brookner really piqued my interest in Digital Signal Processing with his “Kallman Filters as Your Friends” lectures.  Digital signal processing was always fascinating to me and I hoped I could stay on to work on PAC-III, but my role at Raytheon was becoming more towards support for MILSTAR/APATS since it demanded more attention than the PAC-III,  It was too early in my career to settle into this increasing role of supporting projects where you were part of design team.  Observing many of the longer term employees who were at one time designers, it was evident that they overstayed their time and eventually their skills eroded from spending a majority of their time in a support role on projects using antiquated technology.
This was my exit speech to management anyway.    Earlier that year we had a big company-wide and then a division and group-wide motivational sit down pitching this new sexy, satellite-based, wireless personal communications network which permitted any type of telephone transmission including voice, paging, fax of data to reach its destination anywhere on earth.
This we all now know as the Iridium constellation will consist of sixty-six interconnected satellites orbiting 420 nautical miles above the earth.  Unlike the geostationary communications satellites, which are located 22,300 nautical miles above the Earth, the low- earth orbit of Iridium satellites and recent advances in microelectronics makes it possible to communicate with handheld phones.  Twenty-two of these satellites were in orbit as of September 1997.  Each of the sixty- six satellites in the Iridium constellation will project tightly focused beams over the ground.  In effect, the satellites function not unlike extremely tall cellular towers which will provide clear and strong transmissions.
Iridium satellites will be electronically interconnected to provide continuous worldwide coverage. Intersatellite crosslinks make it possible for the satellites to hand off calls between other satellites in the same or adjacent orbiting planes.  Located in key regions of the world, Iridium gateways will interconnect the Iridium satellite constellation to the public switch telephone network.  The Iridium system will employ a combination of “Frequency Division Multiple Access” and ” Time Division Multiple Signal Multiplexing” to make the most efficient use of limited spectrum.  The L- Band ( 1616 – 1626.5 MHz) serves as the link between the satellite and Iridium subscriber equipment.  The Ka- Band (19.4 – 19.6 GHz for downlinks; 29.1 – 29.3 GHz for uplinks) serves as the link between the satellite, gateways and earth terminals.  This network makes communications possible between Iridium telephones and other telephones around the world.  The system has a master control facility, located outside Washington, DC in Northern Virginia, which performs satellite control and network management.  This facility will direct the communications that are relayed via satellite and through terrestrial gateways, where billing information and user location will be stored.  In addition, three telemetries, tracking, and control centers located in Hawaii and Canada are linked with the master control facility.

It was time to move on from Raytheon.  I accepted an offer from White Mountain DSP,  an exciting startup company which did DSP emulators and application boards for TI and Analog Devices (ADI) DSPs. This was a pure design job.  I learned more about programmable hardware, HW/SW integration of DSP systems and was responsible for the board design from concept to release including parts procurement, design, schematic capture, simulation and parts placement on the boards. The routing was contracted out to my requests such as trace lengths and widths, special impedance paths, spacing etc and I would adjust placement as needed.  These boards were simple, being only 6-layer boards and my involvement in board design these days is limited to the FPGA and its peripherals.  In the lab, I will do signal integrity testing and debug of course, but try to leave the board design to the board designers.

While attending UMASS I took a yr long grad level course as part of my required “concentration” (You had to pick 2, I chose control systems and DSP)   The role at WMDSP was mainly designing app boards with the TI FX54x and FX2xx series DSPs including the White Mountain DSP Pathway 2xx DSP Starter Kit (DSK) which made an appearance in the EE times sometime in 1998.

The Dreaded UEVM

Among other projects was a legacy bus Universal Evaluation Module (UEVM) where you could mount a number of TI DSP daughter cards, we made in-house.   It just had all the circuitry a DSP prototype target system would need (at that time.)   It was like an instant prototype target for DSP software guys which back in the day was pretty much all SW driven. One of the last projects was a PCMCIA card for a JTAG boundary scan DSP emulator and pod.  This was my only plug-n-play device to date.  It was for those who wanted to be able to travel with their laptops and continue working on their DSP coding with a portable debugger.  Since it ran on battery the power drawn by this part needed to be down to 300 mA or less.  It was the main hurdle in the development of this product.  WMDSP exclusively used AMD CPLDs at the time of the concept phase of this project’s design lifecycle.  I presented a new design using a Xilinx, low power FPGA and was able to achieve the goal with less than 200 mA of current draw.  We OEM’d this product out to Asset Intertech who used it in their boundary scan test equipment because they were unable to achieve this goal themselves.  As a TI DSP emulator, it was taken over by Gaotek in 2000 sometime after the purchase of WMDSP by ADI.

With the new advancements in FPGAs, the DSP as an Application Specific Standard Product (ASSP as opposed to ASIC) has fallen out of favor due to the cheaply available embedded adder and multiplier structures and now a very advanced set of IP libraries available on FPGAs these days, both fabricated on the FPGA itself or available as compiled libraries.  Just before the cusp of the slow demise of the DSP as the main Application Specific Standard Product (ASSP) for DSP systems and the rise of the modern FPGA, White Mountain, DSP was bought out by ADI and I left shortly thereafter opting for their buyout offer over the generous 5-yr stock option plan offered.   I was excited about the advancement of FPGAs with fabricated multiplier and adder structures on the horizon and knew this would be a better direction to go.  Most of my DSP algorithm experience there was writing some applications in C  and very little in the form of hardware realizations of DSP structures.

After taking the buyout and a few months off to travel around the world, I came back and posted a resume online.  A week later IBM offered made a contract offer to work on their E-beam Lithography research team.  This was a predominantly VHDL/DSP position with some lab time for debugging involved and the prototype was in the good old VME chassis mentioned earlier.   I worked on the Beam Positioning and Timing (BPAT) sub-system and the less sexy work of the VME bus interface from the card, all controlled from the FPGA.  (The ckt board was already designed, so I had no responsibility regarding the board design.  There was some magnetic lensing involved, so my physics background helped with developing the BPAT control system.  At White Mountain DSP I used Xilinx FPGA’s, but at IBM we used an Altera Flex.  This was the first of many consulting jobs which I continue to do to this day.  (With the exception of the last 5 years.)

Electron-beam lithography is a technique that employs a focused beam of electrons in order to pattern a
mask or a silicon wafer.

Electron-beam lithography is a technique that employs a focused beam of electrons in order to pattern a mask or a silicon wafer. The pattern is written directly to the resist by a fast scanning of the high-energy beam onto an electron-sensitive resist. If used directly on a silicon wafer (as opposed to making a mask), this technique is much more precise than photolithography or x-ray lithography because there is no need for a mask. However, e-beam lithography is most commonly used to manufacture high-resolution masks
for photolithography and x-ray lithography. The main advantage of e-beam lithography is that it beats the diffraction limit of light, and as a result, it can produce features as small as 5 nanometers. Additionally, it can be used for low volume production of semiconductor parts. If a chip needs to be unusually precise, e-beam lithography is the best way to make it


Designed the Calibration Test Set for a high-resolution SONAR system front end.  A mixed signal system which generated arbitrary waveforms selected by the user. The user would upload a data file of a waveform to the local memory on the Altera FPGA. The system was also able to detect waveforms generated by the SONAR and return a value in linear or dB format to the front panel. All digital circuitry was designed targeting an Altera FPGA in Quartus including local memory and configurable digital filters. The analog circuitry included A2D, D2A and modulated waveform detection circuitry.

Designed Brushless DC Motor Controller for LRLAP projectile in Lockheed Martin’s AGS System for the Navy Zumwalt class of Destroyers- Designed and implemented the control logic using Finite state machines and RTL in VHDL. Actel ProAsic FPGA target using Libero tools (Synplify and ModelSim) MATLAB used for generating controller transfer function.  Sub designs included UART, pos trackers, ARINC, MIL-STD-1553, DAQ, digital filtering, and PWM generators. Project conformed to RTCA/DO-254 guidelines. DAL-B

Designed Distributed Built-in-Test (BIT) for Mission Management Processor on Boeing’s x45 JUCAS Aircraft for dual-G4 SBC, VME64 system. VME chassis included: Programmable Discrete I/O, Dual G4 SBC, GB Ethernet and PCIe boards Actel ProAsic FPGA on discrete I/O card verified to 98% coverage upon completion of BIT. The project was compliant under Mil-Std for reliability (HBK-HW-55) and BIT Design Process (HBK-SYS-9).

Having enjoyed my time with IBM, the only work I had InterDigital develops fundamental wireless technologies for mobile devices, wireless networks with mobile broadband capabilities with billions of consumers globally.  InterDigital’s focus was wireless bandwidth and network optimization.  Hardware design and development of FPGA based platforms used to verify 3G/4G modem ASIC designs.

Part of a large ASIC Development team for a 2G/3G GSM/CDMA baseband system.

The system was first modeled using a modem board with two processor daughter cards designed in-house. The Modem board interfaced to a Radio interface board with Infineon (Thor) cell phone radio modules.

This modem board contained 2 Startix-II FPGA’s for CHIP and Symbol processing. The layer -1 proc card used a Startix-II FPGA with a softcore embedded ARM9 while the layer 2/3 processor card used a hardcore embedded ARM9 on an Altera Excaliber FPGA.

The modem board and layer-1 processor boards were combined into a single ASIC. In my second year as a consultant there my team designed the verification platform for this ASIC. The second processor board was replaced with a GSM ASIC from Infineon.

As a member of the hardware verification team, tasks included the integration of digital front end IP for 2G/3G dual-mode modem design developed on FPGAs to eventually be fabricated as part of an ASIC.    (The 2G was OEM’d from Infineon and the 3G MODEM was developed at Interdigital on ARM embedded FPGAs)  The hardware platform used to integrate and validate the 3G modem software and later modified to verify the ASIC was itself a separate FPGA based design.  Unit testing and debugging were previously performed using this platform.  FPGA logic design for the platform included Altera Stratix family and Xilinx Virtex family FPGAs using VHDL/Veriliog and performing functional and timing simulation was performed using Mentor Modelsim and of course documentation of design specifications, test procedures and test data.   Most of my time spent there was in the lab for integration test and debugging.  Standard instrumentation was used along with a Rohde-Schwarz Radio Test Set.

After the lengthy (nearly 2-year) contract with interdigital walking through a multi FPGA embedded design from design through integration and release the search for an interesting contract to put those

Designed a real-time FLIR (Forward Looking Infra-Red) video image de-rotation system on a single Virtex-4 FX100 FPGA for Zumwalt class of Navy Destroyers.  RocketIO GTX SERDES, QDRII SRAM, MATLAB, Xilinx ISE, SDK

Rockwell Collins

Senior ConsultantOctober 8, 2011 to November 17, 2012Newport News, Virginia (Formerly ICG, acquired by Rockwell- Collins for $50M August 6, 2015)

Modernization and Redesign of the ICG NxtLink ICS-220A Iridium communications system digital interface (VHDL on a Xilinx CPLD) to conform with DO-254 guidelines.

Responsible for forming the Plan for Hardware Aspects of Certification and writing the planning document (PHAC) which defines the processes, procedures, methods, and standards to be used to achieve the objectives outlined in the DO-254 guidelines.
The above paragraph does not do justice to the amount of work required to complete the planning phase in accordance with the DO-254 guideline.  so you are about to be tortured with a description of what needs to be done in general and what needed to be done in this particular project.  There is a lot of paraphrasing and straight up cut and paste out of the RTCA DO-254 guideline document.  The DO-254 is not a specification, std or set of requirements, it is what it says it is; A Guideline.  Since this is my bio and much career time was spent working within this framework, I would be remiss if I didn’t take some time to discuss DO-254, I’m sorry.

Here’s really where it stands right now in July of 2018: As the speed and bandwidth of these systems has increased, I have narrowed my focus around the FPGA itself and the circuitry which directly interfaces to it and most especially what is going on inside the ‘FPGA including the embedded processors and highly sophisticate IP which all must be integrated successfully both inside the FPGA and with its surrounding peripherals.  The speeds of the SERDES is well into the microwave range now, so my RF/Microwave background is paying dividends.  Most old-school digital and SW guys have no clue about what happens up at those frequencies.  We have Analog to Digital and Digital to Analog converters which are a combination not only of the obvious but they also use DSP technology and there is serious noise analysis involved in comping out the noise of these things.  There are even slower A to D converters built into the FPGAs now, but they are not sufficient for high-speed analog signals like those of many modern sensors, particularly in the aerospace industry.  Delta-Sigma A to D converters is now the norm, very high speed as conversion circuitry goes.  There’s an entire grad class dedicated to these converter circuits.

Xilinx Virtex UltraScale FPGA VCU108 Evaluation Kit

This kit provides an ideal platform for prototyping systems that require massive data flow and packet processing such as 400+ Gbps systems, large-scale emulation, and high-performance computing.
I’m working hard on trying to keep this bio focused on my skill set and especially the details of my experience, not just as a designer, but a scientist and technician too.  These are the qualities I believe make a good member of a laboratory team.   I have always considered myself a scientist as well as an engineer, minoring in Physics and Mathematics at UMASS Amherst.  It was a lot of extra work for an already difficult undergraduate degree.  I am very dedicated, passionate and driven about my career choices having continued my education while working on my own IP these last few years.  The focus was not just on the new technology advances though.  I was able to get several certifications in Xilinx Vivado tools (Such as HLS which is a desired skill for this position) but I have also taken certificate  graduate courses for in Digital Image and Video Processing (this is an advanced DSP class), Computer Architecture (we built a MIPS microprocessor from the ground up using VHDL, the language with which we program the FPGAs), Embedded FPGA Systems (using the Altera MAX-10 with an embedded NIOS microprocessor) and even went back to my rudiments by revisiting classes for core skills in the lower division of the undergrad program such as the digital systems and analog electronics courses which are taught differently now then when I took these classes back in 1991.  To stay up to date with advancing technology, you must maintain a strong rudimentary foundation.
 I hope this bio is successful in demonstrating the detailed knowledge and experience I can bring to any project.  It should also be evident that I am able to quickly pick up skills needed which might not have been encountered in my career as of yet. The needs of a project usually grow and change; therefore, versatility is highly desirable in lab settings.  This is a trait of which I am proud of.

So if you’re still awake, this is what I do,  I eat, live and breathe electronics.  The modern FPGA system contains a broad scope of EE disciplines.  I am either experienced in these disciplines or familiar with all of them.  For those of which I have no actual design experience,  I have 100% confidence that I can pick up without missing a step.  Electronics is my life and in the last 5 years, I have only studied the things that have interested me regarding the latest advances in the field and am so much better for having done it.   If nothing else I’m dedicated.

Thanks for listening if you got this far.