Patrick Donaldson: A Shameless Self Portrait
150 in One Electronic Project Kit
Fender Blues Deluxe Tube Guitar Amp
And now for some foreshadowing. An engineer’s awareness and knowledge of the challenges in the operational environment of space is critical such that the design is tested to the limits of a mission without requiring expensive overdesign. Planning for such designs which use microelectronic components and assemblies in space environments requires adherence to strict guidelines. Much of what was learned by NASA has been passed down to the avionics community. The characteristics of a variety of environments, relevant to both Earth and space scientific, military and commercial missions, are enveloped within typical representative parameters: Radiation, Thermal, Vibration, Electrostatic, Electromagnetic, and Electrical environments. Early on these lessons were learned from working with the MILSTAR program. There are standards and guidelines which must be adhered to. Many companies have their own standards regarding coding style for software and HDL languages, safety procedures and of course design standards (such as design to test etc.)
Then there are Military, Commercial, Medical and other standards, too numerous to mention. My introduction to Design assurance and reliability came as part of the package and I learned it is essential to being a designer of electronic systems. Mil-Std for reliability (MIL-HDBK-217), (HBK-HW-55) and BIT Design Process (HBK-SYS-9) RTCA DO-254
There was some motor controller testing in this group and something called Kalman Filters in the tracking system. These filters have many uses in motion tracking and are great for trajectory optimization for missiles, but also has many other uses such as Econometrics. There was a Principal Engineer Dr. Eli Bruchner on staff at Raytheon who taught a class to our group once a week. This work was at the forefront of signal processing technology.
Dr. Eli Brookner
Taught the Class: “Kallman Filters as Your Friends!”
Eli’s Favorite Circuit!
Iridium satellites will be electronically interconnected to provide continuous worldwide coverage. Intersatellite crosslinks make it possible for the satellites to hand off calls between other satellites in the same or adjacent orbiting planes. Located in key regions of the world, Iridium gateways will interconnect the Iridium satellite constellation to the public switch telephone network. The Iridium system will employ a combination of “Frequency Division Multiple Access” and ” Time Division Multiple Signal Multiplexing” to make the most efficient use of limited spectrum. The L- Band ( 1616 – 1626.5 MHz) serves as the link between the satellite and Iridium subscriber equipment. The Ka- Band (19.4 – 19.6 GHz for downlinks; 29.1 – 29.3 GHz for uplinks) serves as the link between the satellite, gateways and earth terminals. This network makes communications possible between Iridium telephones and other telephones around the world. The system has a master control facility, located outside Washington, DC in Northern Virginia, which performs satellite control and network management. This facility will direct the communications that are relayed via satellite and through terrestrial gateways, where billing information and user location will be stored. In addition, three telemetries, tracking, and control centers located in Hawaii and Canada are linked with the master control facility.
While attending UMASS I took a yr long grad level course as part of my required “concentration” (You had to pick 2, I chose control systems and DSP) The role at WMDSP was mainly designing app boards with the TI FX54x and FX2xx series DSPs including the White Mountain DSP Pathway 2xx DSP Starter Kit (DSK) which made an appearance in the EE times sometime in 1998.
Among other projects was a legacy bus Universal Evaluation Module (UEVM) where you could mount a number of TI DSP daughter cards, we made in-house. It just had all the circuitry a DSP prototype target system would need (at that time.) It was like an instant prototype target for DSP software guys which back in the day was pretty much all SW driven. One of the last projects was a PCMCIA card for a JTAG boundary scan DSP emulator and pod. This was my only plug-n-play device to date. It was for those who wanted to be able to travel with their laptops and continue working on their DSP coding with a portable debugger. Since it ran on battery the power drawn by this part needed to be down to 300 mA or less. It was the main hurdle in the development of this product. WMDSP exclusively used AMD CPLDs at the time of the concept phase of this project’s design lifecycle. I presented a new design using a Xilinx, low power FPGA and was able to achieve the goal with less than 200 mA of current draw. We OEM’d this product out to Asset Intertech who used it in their boundary scan test equipment because they were unable to achieve this goal themselves. As a TI DSP emulator, it was taken over by Gaotek in 2000 sometime after the purchase of WMDSP by ADI.
With the new advancements in FPGAs, the DSP as an Application Specific Standard Product (ASSP as opposed to ASIC) has fallen out of favor due to the cheaply available embedded adder and multiplier structures and now a very advanced set of IP libraries available on FPGAs these days, both fabricated on the FPGA itself or available as compiled libraries. Just before the cusp of the slow demise of the DSP as the main Application Specific Standard Product (ASSP) for DSP systems and the rise of the modern FPGA, White Mountain, DSP was bought out by ADI and I left shortly thereafter opting for their buyout offer over the generous 5-yr stock option plan offered. I was excited about the advancement of FPGAs with fabricated multiplier and adder structures on the horizon and knew this would be a better direction to go. Most of my DSP algorithm experience there was writing some applications in C and very little in the form of hardware realizations of DSP structures.
After taking the buyout and a few months off to travel around the world, I came back and posted a resume online. A week later IBM offered made a contract offer to work on their E-beam Lithography research team. This was a predominantly VHDL/DSP position with some lab time for debugging involved and the prototype was in the good old VME chassis mentioned earlier. I worked on the Beam Positioning and Timing (BPAT) sub-system and the less sexy work of the VME bus interface from the card, all controlled from the FPGA. (The ckt board was already designed, so I had no responsibility regarding the board design. There was some magnetic lensing involved, so my physics background helped with developing the BPAT control system. At White Mountain DSP I used Xilinx FPGA’s, but at IBM we used an Altera Flex. This was the first of many consulting jobs which I continue to do to this day. (With the exception of the last 5 years.)
Electron-beam lithography is a technique that employs a focused beam of electrons in order to pattern a mask or a silicon wafer. The pattern is written directly to the resist by a fast scanning of the high-energy beam onto an electron-sensitive resist. If used directly on a silicon wafer (as opposed to making a mask), this technique is much more precise than photolithography or x-ray lithography because there is no need for a mask. However, e-beam lithography is most commonly used to manufacture high-resolution masks
for photolithography and x-ray lithography. The main advantage of e-beam lithography is that it beats the diffraction limit of light, and as a result, it can produce features as small as 5 nanometers. Additionally, it can be used for low volume production of semiconductor parts. If a chip needs to be unusually precise, e-beam lithography is the best way to make it
Designed the Calibration Test Set for a high-resolution SONAR system front end. A mixed signal system which generated arbitrary waveforms selected by the user. The user would upload a data file of a waveform to the local memory on the Altera FPGA. The system was also able to detect waveforms generated by the SONAR and return a value in linear or dB format to the front panel. All digital circuitry was designed targeting an Altera FPGA in Quartus including local memory and configurable digital filters. The analog circuitry included A2D, D2A and modulated waveform detection circuitry.
Designed Brushless DC Motor Controller for LRLAP projectile in Lockheed Martin’s AGS System for the Navy Zumwalt class of Destroyers- Designed and implemented the control logic using Finite state machines and RTL in VHDL. Actel ProAsic FPGA target using Libero tools (Synplify and ModelSim) MATLAB used for generating controller transfer function. Sub designs included UART, pos trackers, ARINC, MIL-STD-1553, DAQ, digital filtering, and PWM generators. Project conformed to RTCA/DO-254 guidelines. DAL-B
Designed Distributed Built-in-Test (BIT) for Mission Management Processor on Boeing’s x45 JUCAS Aircraft for dual-G4 SBC, VME64 system. VME chassis included: Programmable Discrete I/O, Dual G4 SBC, GB Ethernet and PCIe boards Actel ProAsic FPGA on discrete I/O card verified to 98% coverage upon completion of BIT. The project was compliant under Mil-Std for reliability (HBK-HW-55) and BIT Design Process (HBK-SYS-9).
Having enjoyed my time with IBM, the only work I had InterDigital develops fundamental wireless technologies for mobile devices, wireless networks with mobile broadband capabilities with billions of consumers globally. InterDigital’s focus was wireless bandwidth and network optimization. Hardware design and development of FPGA based platforms used to verify 3G/4G modem ASIC designs.
Part of a large ASIC Development team for a 2G/3G GSM/CDMA baseband system.
The system was first modeled using a modem board with two processor daughter cards designed in-house. The Modem board interfaced to a Radio interface board with Infineon (Thor) cell phone radio modules.
This modem board contained 2 Startix-II FPGA’s for CHIP and Symbol processing. The layer -1 proc card used a Startix-II FPGA with a softcore embedded ARM9 while the layer 2/3 processor card used a hardcore embedded ARM9 on an Altera Excaliber FPGA.
The modem board and layer-1 processor boards were combined into a single ASIC. In my second year as a consultant there my team designed the verification platform for this ASIC. The second processor board was replaced with a GSM ASIC from Infineon.
As a member of the hardware verification team, tasks included the integration of digital front end IP for 2G/3G dual-mode modem design developed on FPGAs to eventually be fabricated as part of an ASIC. (The 2G was OEM’d from Infineon and the 3G MODEM was developed at Interdigital on ARM embedded FPGAs) The hardware platform used to integrate and validate the 3G modem software and later modified to verify the ASIC was itself a separate FPGA based design. Unit testing and debugging were previously performed using this platform. FPGA logic design for the platform included Altera Stratix family and Xilinx Virtex family FPGAs using VHDL/Veriliog and performing functional and timing simulation was performed using Mentor Modelsim and of course documentation of design specifications, test procedures and test data. Most of my time spent there was in the lab for integration test and debugging. Standard instrumentation was used along with a Rohde-Schwarz Radio Test Set.
After the lengthy (nearly 2-year) contract with interdigital walking through a multi FPGA embedded design from design through integration and release the search for an interesting contract to put those
Designed a real-time FLIR (Forward Looking Infra-Red) video image de-rotation system on a single Virtex-4 FX100 FPGA for Zumwalt class of Navy Destroyers. RocketIO GTX SERDES, QDRII SRAM, MATLAB, Xilinx ISE, SDK
Modernization and Redesign of the ICG NxtLink ICS-220A Iridium communications system digital interface (VHDL on a Xilinx CPLD) to conform with DO-254 guidelines.
Here’s really where it stands right now in July of 2018: As the speed and bandwidth of these systems has increased, I have narrowed my focus around the FPGA itself and the circuitry which directly interfaces to it and most especially what is going on inside the ‘FPGA including the embedded processors and highly sophisticate IP which all must be integrated successfully both inside the FPGA and with its surrounding peripherals. The speeds of the SERDES is well into the microwave range now, so my RF/Microwave background is paying dividends. Most old-school digital and SW guys have no clue about what happens up at those frequencies. We have Analog to Digital and Digital to Analog converters which are a combination not only of the obvious but they also use DSP technology and there is serious noise analysis involved in comping out the noise of these things. There are even slower A to D converters built into the FPGAs now, but they are not sufficient for high-speed analog signals like those of many modern sensors, particularly in the aerospace industry. Delta-Sigma A to D converters is now the norm, very high speed as conversion circuitry goes. There’s an entire grad class dedicated to these converter circuits.
Xilinx Virtex UltraScale FPGA VCU108 Evaluation Kit
So if you’re still awake, this is what I do, I eat, live and breathe electronics. The modern FPGA system contains a broad scope of EE disciplines. I am either experienced in these disciplines or familiar with all of them. For those of which I have no actual design experience, I have 100% confidence that I can pick up without missing a step. Electronics is my life and in the last 5 years, I have only studied the things that have interested me regarding the latest advances in the field and am so much better for having done it. If nothing else I’m dedicated.
Thanks for listening if you got this far.